1. Field of the Invention
The present invention relates to a memory device including a semiconductor.
2. Description of the Related Art
As a memory device including a semiconductor, which is used in various electronic products and electronics products, a dynamic random access memory (DRAM), a static random access memory (SRAM), and the like can be given.
In a DRAM, data is stored by holding charge in a capacitor which is provided in a memory cell. However, even when a transistor used for switching is in an off state, a slight amount of leakage current is generated between a source and a drain; thus, the data is lost within a relatively short time (several tens of seconds at the longest). Therefore, the data needs to be rewritten (refreshed) on a regular cycle (generally once every several tens of milliseconds), and power consumption is high even in a standby period.
While miniaturization of a circuit has been attempted, a deep hole (a trench) or a chimney-like projection (a stack) is formed to function as a capacitor because the capacitance of the capacitor needs to be kept constant (generally, 10 fF or higher). With the miniaturization, the aspect ratio thereof (the ratio of height or depth to base) has become 50 or more. A special technique for forming such a structure has been needed (see Non-Patent Document 1 and Non-Patent Document 2).
In an SRAM, data is held by utilizing a bistable state of a flip-flop circuit. When a CMOS inverter (a complementary inverter) is used in a flip-flop circuit of an SRAM, the amount of power consumption in a standby period is significantly smaller than that of a DRAM (see Patent Document 1). Therefore, an SRAM is used instead of a DRAM for applications, e.g., a cellular phone, in which the frequency of data writing and data reading is not so high and a standby period is much longer than a period during which data writing and data reading are performed. However, since six transistors are used in one memory cell, the degree of integration is lower than that of a DRAM and the unit cost per bit is ten times or more as high as that of the DRAM.
In recent years, a transistor in which the amount of leakage current between a source and a drain in an off state is extremely small and which has excellent charge holding characteristics has been devised, and a memory cell using it has been proposed (see Patent Document 2). In the case where a transistor of this structure is used, two transistors are needed for one memory cell; however, a capacitor having large capacitance is not needed unlike in a DRAM. In addition, data can be held for an extremely long period without refresh operation.